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IR3865MPBF
LAYOUT RECOMMENDATIONS
Bypass Capacitor:
As VCC bypass capacitor, a 1μF high quality
ceramic capacitor should be placed on the same
side as the IR3865 and connected to VCC and
PGND pins directly. A 1μF ceramic capacitor
should be connected from 3VCBP to AGND to
avoid noise coupling into controller circuits. For
single-ground designs, a resistor (R12) in the
range of 5 to 10 Ω in series with the 1μF
capacitor as shown in Figure 7 is recommended.
Boot Circuit:
C BOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
upper MOSFET turns on.
Power Stage:
Figure 27 shows the current paths and their
directions for the on and off periods. The on time
path has low average DC current and high AC
current. Therefore, it is recommended to place
the input ceramic capacitor, upper, and lower
MOSFET in a tight loop as shown in Figure 27.
The purpose of the tight loop from the input
ceramic capacitor is to suppress the high
frequency (10MHz range) switching noise and
Q1
IR3865
Q2
Figure 27. Current Path of Power Stage
reduce Electromagnetic Interference (EMI).
If
this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase
the switching loss. The off time path has low AC
and high average DC current. Therefore, it
should be laid out with a tight loop and wide
trace at both ends of the inductor. Lowering the
loop resistance reduces the power loss. The
typical resistance value of 1-ounce copper
thickness is 0.5 mΩ per square inch.
8/8/2012 Rev3.1
18
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